2018-004 An Efficient Architecture to Compute Sparse Neural Network

SUMMARY

UCLA researchers in the Department of Electrical Engineering have developed a novel hardware architecture for computing sparse neural networks.

BACKGROUND

Sparse neural networks (SNNs, or a neural network in which most matrices’ entries are zeros), are used to reduce the number of matrix coefficients, leading to more efficient storage and computations. However, the recently reported NN hardware accelerator cannot compute SNN due to its inability to bypass computation of zero in dataflow. There is a need for neural network architecture that can process and benefit from SNNs.

INNOVATION

Researchers at UCLA have developed an efficient hardware architecture for computing SNNs. The architecture achieves this by using a unique data organization system that allows both zero- and non-zero weights to be stored and later reconstructed using relative address coding. This allows processing of SNNs without the usual downfall of attempting to compute zero in dataflow. This architecture also enables computation of dense networks by a similar process.

POTENTIAL APPLICATIONS

• Hardware architecture to compute sparse neural networks
• Computation of dense networks

ADVANTAGES

• Overcomes previous inability of hardware accelerator to compute sparse networks
• Can be applied to both sparse and dense neural networks
• Reduces power consumption during computation through data reuse

RELATED MATERIALS

•  L. Du, Y. Du, Y. Li, J. Su, Y.-C. Kuan, C.-C. Liu, M.-C.F. Chang, A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, IEEE Transactions on Circuits and Systems I, 2018.

PATENT STATUS

United States of America       Published Patent Application       20210042610       02/11/2021