2020-770 Apparatus and Method for Changing the Functionality of an Integrated Circuit Using Charge Trap Transistors

SUMMARY

UCLA researchers in the Department of Electrical and Computer Engineering have developed a method to overcome manufacturing defects in semiconducting wafers through post-production calibration of integrated circuits by threshold voltage tuning using charge trap transistors. 

BACKGROUND

Complementary metal-oxide-semiconductors (CMOS) are utilized for the generation of integrated circuits used in devices such as memory chips, microprocessors, and other digital/analog circuits. Miniaturization of CMOS circuits produces smaller transistors which are faster and more power efficient. However, reduction in size often results in fabrication defects which can negatively impact the performance of the resulting chip and significantly reduce production yield. Methods to overcome these defects and calibrate the performance of CMOS wafers post-production are therefore vital to increase yield and decrease cost.

INNOVATION

UCLA researchers in the Department of Electrical and Computer Engineering have developed a method to increase CMOS wafer yield through post-production modification. Enhancement in performance is achieved through calibrating the threshold voltage of a transistor by charge trapping. Importantly, this method does not incorporate any additional fabrication steps which are lengthy and costly. Overall, enhanced utility of produced CMOS wafers could result in significant downstream cost reduction of consumer electronics.

POTENTIAL APPLICATIONS

• Electronics
• Memory devices
• Servers
• Computers and tablets
• Wearable Electronics

ADVANTAGES

• Reduces transistor mismatch electronically in post-fabrication
• Fine tunes circuit parameters in a non-volatile fashion
• Extra fabrication steps are not required
• Higher effective yield of produced CMOS wafers

RELATED MATERIALS

• Nouri, Sepideh and Iyer, Subramanian S., “Non-Volatile Wideband Frequency Tuning of a Ring-Oscillator by Charge Trapping in High-k Gate Dielectric in 22nm CMOS” IEEE Electron Device Letters (2020), In press.
• Gu, Xuefeng et al. “Charge-trap transistor for CMOS-Only analog memory” IEEE T Electron Dev (2019) 66, 10: 4183-4187.

STATUS OF DEVELOPMENT

First successful demonstration (first actual reduction to practice)