Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel analog-digital conversion (ADC) Architecture that achieves high-speed, high-resolution signal conversion with reduced power consumption and increased linearity.
Background:
High-speed, high-resolution analog-digital converters (ADCs) are what allow modern electronics to display real-world-derived signals, making them a necessity in communication systems and consumer devices. Contemporary ADCs struggle to achieve high-speed and high-resolution conversion simultaneously, especially when constrained by power efficiency and linearity (complexity). As data-intensive applications like high-speed communication, medical imaging and artificial intelligence burgeon, there is an escalating demand for ADCs that efficiently push the boundaries of speed and resolution.
Innovation:
UCLA researchers have developed a novel ADC architecture that more efficiently resolves complex analog data. Their design achieves an overall 8-bit resolution with 1 bit of redundancy. The completely dynamic design has reduced linearity requirements compared to devices with similar resolutions because each stage operates in parallel; multiple ADCs can be pipelined, increasing the speed of operation. No linear amplifiers are used, reducing power consumption and complexity. This new fully digital ADC architecture presents a significant leap in ADC design that is scalable as the underlying digital processing technology advances.
Press Release:
The inventors won the Qualcomm Innovation Fellowship for North America in 2023: https://www.qualcomm.com/research/university-relations/innovation-fellowship/winners
Potential Applications:
• Telecommunications
• Medical Imaging
• Wireless sensors & IoT devices
• Automotive sensors like LIDAR and RADAR
• Scientific instruments, i.e. spectrometers & radio telescopes
• Audio and visual processing
• High-frequency financial trading systems
Advantages:
• Relaxed linearity requirements
• Reduced Time-to digital Converter (TDC) full-scale range
• Absence of linear amplifiers, reducing power consumption and complexity
• 8-bit resolution with 1 bit of redundancy
State of Development:
The inventors have proposed and modeled the new architecture and are demonstrating its efficacy in silico.
Reference:
UCLA Case No. 2023-276
Lead Inventor:
Behzad Razavi, UCLA Professor of Electrical and Computer Engineering