Summary:
Researchers in the UCLA Department of Electrical and Computer Engineering have developed an energy efficient neuromorphic computing architecture.
Background:
Widespread growth in demand for artificial intelligence systems has highlighted limitations in current central processing unit (CPU) designs, particularly in terms of energy efficiency and scalability. The rapid rise in generative AI and natural language processing applications over the past several years has significantly amplified the need for highly-efficient computing systems. New architectures, like neuromorphic computing systems, have emerged to address this issue. Neuromorphic computing aims to achieve energy efficiency by implementing brain-like mechanisms for computation and learning. Spike neural networks (SNNs) are a core component of neuromorphic systems and use event-driven computation to reduce energy consumption by processing sparse, spike-based data. However, challenges remain in balancing power efficiency, performance, and hardware implementation of these systems for real-world applications.
Innovation:
Researchers led by Professor M. C. Frank Chang have developed a novel neuromorphic computing system to address these challenges. They leverage three innovative components; latency encoding for efficient spike representation, a compute-in-memory module via analog matrix multiplication, and a novel event-driven integrate and fire (EIF) neuron that eliminates the need for high resolution analog to digital converters (ADCs). This innovative architecture achieves precise spike generation and significantly improved energy efficiency, paving the way for scalable, high-performance neuromorphic hardware systems.
Potential Applications:
• Neuromorphic computing
• Brain machine interfaces
• Real-time object detection/recognition
• Artificial intelligence and machine learning optimization
• Autonomous vehicle navigation
• Robotics and automation
• Pattern recognition for security, surveillance and defense applications
Advantages:
• High energy efficiency
• Low latency
• Hardware scalability
• ADC-free design
Development-To-Date:
Researchers have developed the circuit design in silico and performed simulated computation.
Reference:
UCLA Case No. 2024-275
Lead Inventor:
Distinguished Professor M. C. Frank Chang, UCLA Department of Electrical and Computer Engineering