UCLA researchers have invented a method and circuit architecture for fine-grained power gating within FPGA (field-programmable gate array) interconnects. By selectively disabling (power gating) unused multiplexers and routing segments at a fine granularity, the approach reduces leakage power in FPGA interconnects while preserving performance and flexibility.
In modern FPGAs and programmable logic devices, much of the silicon area is used for interconnect routing (multiplexers, switches, wiring). Even when routing paths are unused, static leakage and parasitic capacitance cause wasted energy. Traditional power gating techniques often work at coarse granularity (entire blocks or macros), but lack flexibility to turn off unused interconnect segments without disrupting routing flexibility. There is a need for power-reduction techniques at the interconnect level that are fine-grained, dynamically configurable, and compatible with FPGA logic/routing architectures.
The invention embeds power gating control signals (PG_EN) into static multiplexers used in FPGA interconnect logic. These multiplexers include a standard selection logic plus an additional power gating enable input.
When a multiplexer is not in use (i.e. its input is not selected), the power gating control disables (turns off) parts of the multiplexer’s output driver (e.g. via a PMOS transistor in cutoff mode) to cut leakage current.
The design separates supply voltages (e.g. a high domain VDDH and a lower domain VDDL) to control logic and gating, enabling the gate of a PMOS transistor to be driven with minimal overhead while leaving routing logic dormant when unused.
The architecture supports fine-grained, selective gating of small interconnect segments—multiplexers, inverters, and local routing switches—rather than coarse blocks.
The invention is applicable not just inside FPGAs but to more general logic, configurable routing, or network-on-chip (NoC) systems with routing switches.
Reduces static (leakage) power consumption in the interconnect network, which is significant in scaled modern FPGAs.
Operates at fine granularity: power gating can be applied at individual muxes or small routing elements rather than entire blocks.
Minimal impact on performance: when active, gating is disabled and logic operates normally.
Compatible with existing FPGA routing architectures and programmable logic design flows.
Dynamic control: routing configuration logic can enable/disable gating based on use or mode, allowing runtime adaptation.
Broad applicability to configurable logic, SoCs, and interconnect-heavy circuits beyond just FPGAs.
FPGA vendors seeking to reduce power consumption in their devices, especially in low-power or battery-powered contexts.
Embedded systems and applications where static/leakage power is a major constraint (e.g. IoT, edge devices).
SoC or NoC routing fabrics where routing switches are a large fraction of area and leakage.
Reconfigurable computing platforms where resource usage is dynamic and idle interconnect should be gated.
Power-aware design of configurable logic in data centers, AI accelerators, and reconfigurable hardware.
US 9,923,555 B2 — Fine-Grained Power Gating in FPGA Interconnects Fine-Grained Power Gating in FPGA Interconnects (US9923555B2) Google Patents