| A Radix-3 Network Architecture for Boundary-Less Hierarchical Interconnects (Case No. 2013-162)
                SummaryUCLA researchers have developed a method for designing and implementing boundary-less hierarchical interconnect networks — switching architectures that reduce path length and routing complexity by transforming conventional hierarchical switch networks into “boundary-less” (or more flexible radix) topologies, enabling improved connectivity, lower latency, and more efficient routing in circuits such as FPGAs, SoCs, or reconfigurable logic fabrics. BackgroundIn modern digital integrated systems—FPGAs, system-on-chip (SoC) interconnects, reconfigurable fabrics—hierarchical switch networks (e.g. fat-trees, Benes networks) are used to connect many computing elements (CEs). Hierarchical designs simplify layout, reuse, and scaling, but suffer from fixed radix/structure constraints: signal paths can be long, routing congestion or over-provisioning is needed, and some connections must traverse many intermediate stages, increasing delay and energy. There is a need for more flexible interconnect architectures that reduce latency, wiring length, and switch count while preserving non-blocking connectivity and scalability. Innovation
	
	The invention defines methods to transform traditional hierarchical switch network topologies into boundary-less, radix-flexible switch networks. That is, by pruning under-used switches, relocating cross-routes, and introducing more direct routing paths, parts of the interconnect network become more adaptive, avoiding rigid hierarchical boundaries.
	For example, cross-routing tracks (connections between switches) typically assigned to later stages may be moved or routed earlier in the hierarchy to avoid long detours, thereby reducing path length.
	The architecture supports dynamic reconfiguration of switch networks such that every computing element can connect to every other via fewer stages or more direct routes.
	The approach applies to reconfigurable logic fabric (e.g. FPGAs) or any switch network of computing elements, allowing layout and wiring optimizations, stage reduction, and better performance. Advantages
	
	Reduced latency, as signals traverse fewer switch stages on average.
	Reduced wire length and routing complexity, leading to lower delay and potentially lower power (fewer parasitic losses).
	Less over-provision of switches; some switches or routing stages can be pruned when not needed.
	More uniform or balanced connectivity, reducing bottlenecks in hierarchical interconnects.
	Improved scalability: as computing element count grows, the benefit of boundary-less routing increases.
	Applicable to many types of logic/interconnect fabrics: FPGAs, reconfigurable systems, custom networks-on-chip. Potential Applications
	
	FPGA design and interconnect fabrics, improving performance and reducing power in programmable logic devices.
	System-on-Chip (SoC) routers or interconnect backbones in multicore processors, AI accelerators.
	Communications or data-center hardware where many processing elements must exchange messages with low latency.
	Custom network architectures in mixed hardware/FPGA designs, or heterogeneous computing platforms.
	Reconfigurable hardware used in high-performance computing (HPC) or edge computing that must balance flexibility, latency, and power. Patent / ApplicationUS 9,817,933 B2 — Systems and methods for switching using hierarchical networksSystems and methods for switching using hierarchical networks (US9817933B2) Google Patents
 
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