Summary:
UCLA researchers in the Department of Mechanical and Aerospace Engineering have developed a novel method for producing electrically insulating, high–thermal conductivity through-glass vias.
Background:
Advanced semiconductor systems rely on 3D integrated circuits (3DICs) to meet rising demands for higher performance, reduced form factor, and lower latency. Glass interposers and substrates are being adopted for advanced packaging systems due to their low cost and favorable electrical properties. Unlike the current standard of silicon, glass has low thermal conductivity, which significantly limits heat dissipation. To mitigate this limitation, traditional approaches utilize copper-filled through-glass vias (TGVs) to create vertical heat conduction paths. The mismatch in thermal expansion coefficients between copper and glass introduces large thermal stresses, often leading to delamination or cracking. Additionally, copper-filled TGVs are electrically conductive, limiting their use as dedicated thermal conduits in applications requiring electrical isolation. To improve heat dissipation performance of next generation electronic systems, there is a need for a vertical heat path solution that is both thermally conductive and electrically insulating within glass interposers.
Innovation:
Researchers at UCLA have developed a method for the fabrication, insertion, and bonding of material having high thermal conductivity within TGVs, forming electrically insulating vertical thermal conduits. The design creates continuous heat conduction channels that enable efficient heat dissipation without inducing thermal stress. Compared to conventional glass interposers, the technology achieves a 20x improvement in through-plane thermal conductivity. Additionally, electrical insulation of the vertical thermal conduits enables independent routing of signals and power, increasing design flexibility and preserving signal integrity. The resulting interposer integrates seamlessly into advanced packaging architectures and metal redistribution layers, delivering multifunctional capabilities. It enables direct deployment as a thermally enhanced substrate for high-power integrated circuits, chiplet architectures, and optoelectronic modules. This approach enables superior heat dissipation accompanied by electrical insulation, addressing a key bottleneck in glass-based 3DIC packaging and enabling next-generation semiconductor systems.
Potential Applications:
● High-power logic applications
○ GPUs, TPUs, AI accelerators
○ Improved performance-per-watt
● 3DIC
● RF, mmWave, wireless modules
● Optoelectronics and Photonics
○ Waveguides
● Advanced memory systems
Advantages:
● Heat Dissipation
● Electrical Insulation
● Thermo-mechanical stability
○ Reduced mechanical stress from conductivity mismatches
● Scalable
○ Integratable with glass interposers
○ RDLs
● Maintains glass interposer benefits
○ Low RF loss
○ Dimensional stability
Development-To-Date:
First description of the complete invention; design has been proven through simulations.
Related Papers:
[1] Y. Yang, J. Chien, S. Lyu and T. Wei, "Development of Straight, Small-Diameter, High-Aspect Ratio Copper-Filled Through-Glass Vias (TGV) for High-Density 3D Interconnections," 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, TX, USA, 2025, pp. 1036-1042, doi: 10.1109/ECTC51687.2025.00181.
Reference:
UCLA Case No. 2026-157
Lead Inventor:
Tiwei Wei, Assistant Professor, Department of Mechanical and Aerospace Engineering