Background:
Due to their chemical makeup and heat generation, devices such as high-k/metal gate (HKMG) CMOS often accumulate charges can lead to variation in integrated circuits. Charge Trap Transistors (CTT's) utilize accumulating charge in semiconducting devices as embedded non-volatile memory (eNVM). The introduction of CTT's can prove an invaluable tool for manufacturers, allowing them to turn stock logic transistors into multi-time programmable (MTP) non-volatile memory elements that operate at logic compatible voltages without the need for any additional processes or masks.
2021-167 Non-Volatile SRAM Using Charge Trap Transistors
Innovation: UCLA researchers in the Department of Electrical and Computer Engineering have designed an embedded non-volatile SRAM (nvSRAM), using Charge Trap Transistors (CTT) in a CMOS logic process, without any extra fabrication steps (such as floating gate). Because of its unique design, it can rapidly store data on chip and then quickly power down or enter a lower power mode as necessary. For example, when the memory is idle, its power supply can be turned OFF to eliminate the leakage power consumption by the idle memory. Once the power is back ON, memory can recall the original data. This design can be used as both regular SRAM and an embedded non-volatile memory (NVM) for IoT devices, implantable medical devices, systems that rely on power harvesting and see fluctuations in their power supply, and systems that work based on intermittent-computing methodology.
Applications:
- Low-power-budget devices
- CMOS Logic-based embedded non-volatile memory
- IoT sensors
- Medical devices
- Power supply fluctuation resilient memory
Advantages:
- Stores data despite power loss
- Can be used in designs with a low power budget or a fluctuating power supply
- Area efficient
- Implemented in a CMOS logic-process with no extra fabrication step
- Can be implemented in advanced nodes
2020-770 Apparatus and Method for Changing the Functionality of an Integrated Circuit Using Charge Trap Transistors
Innovation: Complementary metal-oxide-semiconductors (CMOS) are utilized for the generation of integrated circuits used in devices such as memory chips, microprocessors, and other digital/analog circuits. Miniaturization of CMOS circuits produces smaller transistors, which are faster and more power efficient. However, reduction in size often results in fabrication defects which can negatively impact the performance of the resulting chip and significantly reduce production yield. Methods to overcome these defects and calibrate the performance of CMOS wafers post-production are therefore vital to increase yield and decrease cost. UCLA researchers in the Department of Electrical and Computer Engineering have developed a method to increase CMOS wafer yield through post-production modification. Enhancement in performance is achieved through calibrating the threshold voltage of a transistor by charge trapping. Importantly, this method does not incorporate any additional fabrication steps which are lengthy and costly. Overall, enhanced utility of produced CMOS wafers could result in significant downstream cost reduction of consumer electronics.
Applications:
- Electronics
- Memory devices
- Servers
- Computers and tablets
- Wearable Electronics
Advantages:
- Reduces transistor mismatch electronically in post-fabrication
- Fine tunes circuit parameters in a non-volatile fashion
- Extra fabrication steps are not required
- Higher effective yield of produced CMOS wafers
2021-125 Analog Nonvolatile Memory-Based In-Memory Computing Multiply-And-Accumulate (MAC) Engine
Innovation: UCLA researchers led by Professor Iyer have developed a method to use Charge-Trap Transistors (CTTs) for analog nonvolatile memory-based multiply-and accumulate (MAC) systems. This novel method results in a system with reliable and nonvolatile weight storage, low power consumption, and high-throughput computation. The innovation improves system performance as it bypasses the von Neuman memory bottlenecks that prevented high performance. Furthermore, this technology's unique integration with CTT’s, which have significantly lower power consumption, makes it ideal for battery powered edge devices and devices used to enter core networks. The developed method could be utilized to compute fully connected layers in neural networks as well as more complex networks such as Convolutional Neural Network (CNN) layers for AI.
Applications:
- AI computing
- Non-volatile memory usage
- Machine learning processing
- High performance computation
- Bioinformatics
Advantages:
- Non-volatile memory
- High throughput computation
- High performance computations
- Low integration cost
- Complementary Metal Oxide Semiconductor (CMOS) compatibility
- Low device variance
- Excellent charge retention
2016-799 A Plastic Synapse Based on Self-Heating-Enhanced Charge-Trapping in High-K Gate Dielectrics of Advanced-Node Transistors
Innovation: Researchers at UCLA designed a novel way to implement synapses by utilizing advanced-node transistors which show charge-trapping behaviors in high-k gate dielectrics. Only three such transistors are needed to implement a single synapse. In addition, the conductance of the synapse can be tuned over more than two orders of magnitude. The synapse device, combined with complementary metal-oxide semiconductor (CMOS) neuron and control circuits, provides an adaptive learning and large-scale neuromorphic system.
Applications:
- Physical implementation of neuromorphic computers
- Pattern recognition, including images and speech processing
- Smart robotics and self-driving cars that can understand and interact with the world in humanlike ways
- Medical sensors and devices that track individuals’ signs over time, learning to adjust dosages or even catch problems early
- Smartphone applications that learn to anticipate what the user wants next
- Neuromorphic chips for the study of neuroscience and brain
Advantages:
- Highly compact (3-transistor for one synapse)
- Compatibility with large-scale integration (can be implemented by multiple existing transistor technologies)
- Highly uniform
- Highly reliable
- Highly scalable
- No extra material or process complexity
- Capable of different learning behaviors by different signaling schemes
1. F. Khan, E. Cartier, J. C. S. Woo and S. S. Iyer, "Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- k -Metal-Gate CMOS Technologies," in IEEE Electron Device Letters, vol. 38, no. 1, pp. 44-47, Jan. 2017, doi: 10.1109/LED.2016.2633490.