2021-167 Non-Volatile SRAM Using Charge Trap Transistors

SUMMARY

UCLA researchers in the Department of Electrical and Computer Engineering have developed a fast embedded memory using a standard CMOS logic process that can retain data when the powered down for any reason.

BACKGROUND

In traditional static random-access memory (SRAM), data can be lost when the power supply falls below a certain voltage level. To prevent the data loss, the supply voltage of the memory needs to be maintained above a certain level at all times even when memory is idle. This will increase the memory power consumption and can cause issues in low-power applications and in applications with a low memory activity rate. While there are memories that are non-volatile, these memories require special processes and/or materials and operating conditions (such as high voltage) that may not be CMOS logic compatible.  They also tend to be of lower performance.  Hence, there is a need for a fast memory that can keep its data when the power is turned OFF. Such a memory can be used in IoT devices, implantable medical devices, systems that rely on power harvesting and see fluctuations in their power supply, and systems that work based on intermittent-computing methodology.

INNOVATION

UCLA researchers in the Department of Electrical and Computer Engineering have designed an embedded non-volatile SRAM (nvSRAM), using Charge Trap Transistors (CTT) in a CMOS logic process, without any extra fabrication steps (such as floating gate). Because of its unique design, it can rapidly store data on chip and then quickly power down or enter a lower power mode as necessary. For example, when the memory is idle, its power supply can be turned OFF to eliminate the leakage power consumption by the idle memory. Once the power is back ON, memory can recall the original data. This design can be used as both regular SRAM and an embedded NVM for the above-mentioned applications.

POTENTIAL APPLICATIONS

• Low-power-budget devices
• CMOS Logic-based embedded non-volatile memory
• IoT sensors
• Medical devices
• Power supply fluctuation resilient memory

ADVANTAGES:

• Stores data despite power loss
• Can be used in designs with a low power budget or a fluctuating power supply
• Area efficient
• Implemented in a CMOS logic-process with no extra fabrication step
• Can be implemented in advanced nodes

Development to Date:

This innovation has been designed and is being prototyped.

Related Papers:

• F. Khan, E. Cartier, J. C. S. Woo and S. S. Iyer, "Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- κ -Metal-Gate CMOS Technologies," in IEEE Electron Device Letters, vol. 38, no. 1, pp. 44-47, Jan. 2017, doi: 10.1109/LED.2016.2633490.
• S. Nouri and S. Iyer, "Non-Volatile Wideband Frequency Tuning of a Ring-Oscillator by Charge Trapping in High-k Gate Dielectric in 22nm CMOS," IEEE Electron Device Letters, doi:10.1109/LED.2020.3036080.
• S. Nouri and J. R. Cavallaro, "A Supply Fluctuation Resilient SRAM," 2018 52nd Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 2018, pp. 246-250, doi: 10.1109/ACSSC.2018.8645305.
• S. Nouri, B. Aazhang, M. Razavi and J. R. Cavallaro, "A low-power digital ASIC for detecting heart-rate and missing beat," 2017 51st Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, 2017, pp. 1342-1346, doi:10.1109/ACSSC.2017.8335572