Search Results - subramanian+iyer

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A High Throughput Thermal Compression Bonding Scheme for Interposer and Wafer-Scale Advanced Packaging Constructs (Case No. 2023-144)

Summary: UCLA researchers in the Department of Electrical and Computer and Engineering have introduced a scalable and rapid bonding method for dielet assembly on advanced packaging constructs, achieving a remarkable throughput of over 1100 units-per-hour, or 10-fold higher than the conventional assembly method. Background: In semiconductor packaging,...

Published: 7/9/2024 | Inventor(s): Subramanian Iyer, Krutikesh Sahoo, Haoxiang Ren

Keywords(s): advanced packaging, advanced packaging constructs, dielet assembly, dielet bonding, Electronic Packaging, electronics packaging, Fabrication Technologies, face-to-face heterogeneous dielet bonding, heterogeneous integration, heterogenous electronic systems, high throughput, Instrumentation, Interposers, Microelectronics Semiconductor Device Fabrication, Organic Semiconductor, package scaling, Semiconductor, semiconductor chip foundries, Semiconductor Device, Semiconductor Device Fabrication, Semiconductors, thermal compression bonding, wafer-scale, wafer-scale computing, Waferscale Processors

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Waferscale Computing, Materials, Materials > Semiconducting Materials, Materials > Fabrication Technologies, Electrical > Instrumentation

2021-229 Processes, Equipment and Materials Recipes, and Related Know-How to Perform the Silicon-Interconnect Fabric (Si-IF) Chip-Scale Packaging Technology

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel manufacturing process for Silicone-Interconnect Fabric (Si-IF) that is not only scalable, but also robust as it relies on established processing techniques from CMOS technologies. Background: With the rise of computation-heavy applications, such...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Analogue Electronics, CMOS, Consumer Electronics, Digital Electronics, Electronic Packaging, Electronics & Semiconductors, electronics packaging, heterogenous electronic systems, Integrated Circuit Via (Electronics), Interposers, Nanotechnology, Power Electronics, Printed Circuit Board, Printed Electronics, Silicon

Category(s): Electrical, Electrical > Electronics & Semiconductors, Materials, Materials > Nanotechnology, Electrical > Electronics & Semiconductors > Memory

2022-241 A TSV-Less Architecture for Power Delivery and I/O for Interposers and Other Advanced Packaging Constructs

Summary: UCLA researchers led by Professor Iyer have developed a wafer-scale processor manufacturing method that does not require standard through-silicon vias (TSVs). Background: With the rise of machine learning applications, demand for devices capable of high-performance computing (HPC) has also increased. Popularity and demand for wafer-scale...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer, Haoxiang Ren, Saptadeep Pal

Keywords(s): Amorphous Silicon, Artifical Intelligence (Machine Learning, Data Mining), Artificial Intelligence, Artificial Neural Network, Bandwidth (Signal Processing), Brain-Computer Interface, Brain-Computer Interface Body Mass Index, Chipset, Clock Signal, Computer Aided Design & Manufacturing, Computer Aided Learning, Computer Architecture, Computer Monitor, Computer Security, Computer Virus, Computer Vision, Computer-Aided Design, Computer-Aided Diagnosis, Continuum Mechanics Computer Graphics Collision Detection, Digital Signal Processing, Doping (Semiconductor), Electrical, Electrical Engineering, Electrical Impedance, Electrical Load, Electrical Resistance And Conductance, Electrical Resistivity And Conductivity, Electronics & Semiconductors, Graphics Processing Unit, Graphics Processing Unit Analog Computer, Human-Computer Interaction, Machine Learning, Machine Vision, Manufacturing, Microelectronics Semiconductor Device Fabrication, Microprocessor, Network Analysis (Electrical Circuits), Network On A Chip, Organic Semiconductor, Quantum Computer, Semiconductor, Semiconductor Device, Semiconductor Device Fabrication, Semiconductor Ohmic Contact, Semiconductor Risk Assessment, Semiconductor Sapphire, Semiconductors, Signal Processing, Silicon, Silicon Dioxide, Silicon Working Electrode Perovskite (Structure), Silicon-Germanium, Supercomputer, System On A Chip, Tablet Computer

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Signal Processing, Materials > Semiconducting Materials, Electrical > Electronics & Semiconductors > Circuits, Software & Algorithms > Artificial Intelligence & Machine Learning

Silicon Interconnect Fabric (Si-IF) Technologies - Subramanian Iyer

Background: Over the past two decades, silicon chips have decreased in size by 1000x, while packages on circuit boards have only shrunk by 4x. This will eventually limit scaling of integrated circuits and subsequent processor performance. A solution is the invention of platforms for packageless integration of heterogeneous dies, such as silicon interconnect...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Amorphous Silicon, Antenna (Radio) Flip Chip DisplayPort, Application-Specific Integrated Circuit, Bandwidth (Signal Processing), Bandwidth (Signal Processing) RF Transmitters, Brain-Computer Interface, Brain-Computer Interface Body Mass Index, Chipset, Computer Aided Design & Manufacturing, Computer Aided Learning, Computer Architecture, Computer Monitor, Computer Security, Computer Virus, Computer Vision, Computer-Aided Design, Computer-Aided Diagnosis, Continuum Mechanics Computer Graphics Collision Detection, Digital Signal Processing, Doping (Semiconductor), Electrical, Electrical Brain Stimulation, Electrical Breakdown, Electrical Engineering, Electrical Impedance, Electrical Load, Electrical Load Equation Of State, Electrical Resistance And Conductance, Electrical Resistivity And Conductivity, Electronics & Semiconductors, Enzyme Substrate (Biology), Graphics Processing Unit, Graphics Processing Unit Analog Computer, Human-Computer Interaction, Image Processing, Integrated Circuit, Integrated Circuit Standing Wave, Integrated Circuit Via (Electronics), Lab-On-A-Chip, Microelectronics Semiconductor Device Fabrication, Microprocessor, Mixed-Signal Integrated Circuit, Monolithic Microwave Integrated Circuit, Network Analysis (Electrical Circuits), Network On A Chip, Organic Semiconductor, Photonic Integrated Circuit, Printed Circuit Board, Process Optimization, Quantum Computer, Semiconductor, Semiconductor Device, Semiconductor Device Fabrication, Semiconductor Ohmic Contact, Semiconductor Risk Assessment, Semiconductor Sapphire, Semiconductors, Short Circuit, Signal Processing, Silicon, Silicon Dioxide, Silicon Working Electrode Perovskite (Structure), Silicon-Germanium, Substrate (Chemistry), Supercomputer, System On A Chip, Tablet Computer, Three-Dimensional Integrated Circuit, Transcutaneous Electrical Nerve Stimulation, zzsemiconducting materials

Category(s): Electrical, Electrical > Electronics & Semiconductors, Materials, Materials > Semiconducting Materials, Medical Devices, Medical Devices > Coatings

Charge Trap Transistors - Subramanian Iyer

Background: Due to their chemical makeup and heat generation, devices such as high-k/metal gate (HKMG) CMOS often accumulate charges can lead to variation in integrated circuits. Charge Trap Transistors (CTT's) utilize accumulating charge in semiconducting devices as embedded non-volatile memory (eNVM). The introduction of CTT's can prove an...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Charge Carrier, CMOS, Dynamic Random-Access Memory, Electrical, Electrical Engineering, Electrical Load, Electrical Resistance And Conductance, Logic Gate, Magnetoresistive Random-Access Memory, Medical Device, Memory, Power Electronics, Power Transmission, Programmable Logic Device, Random-Access Memory, Resistive Random-Access Memory, Semiconductor Device, Semiconductor Device Fabrication, Static Random-Access Memory, Transistor

Category(s): Electrical, Electrical > Electronics & Semiconductors > Memory, Electrical > Electronics & Semiconductors

2021-125 Analog Nonvolatile Memory-Based In-Memory Computing Multiply-And-Accumulate (MAC) Engine

Summary: UCLA researchers in the Department of the Electrical and Computer Engineering have developed a method to use Charge-Trap Transistors (CTTs) for analog nonvolatile memory-based in memory computing multiply-and accumulate (MAC) engine for high performance computations in AI platforms. Background: Advances in Machine Learning and Artificial...

Published: 10/26/2023 | Inventor(s): Subramanian Iyer

Keywords(s):

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Memory

2021-187 Post-Process Testing Station for Semiconductor Device Fabrication

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a system that can perform electrical and optical tests on semiconductor devices in a non-destructive fashion. Background: Modern electronic devices require the usage of semiconductors which need to be produced in a uniform way and evaluated to ensure...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer, Subramanian Iyer

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Category(s): Electrical > Sensors, Electrical > Electronics & Semiconductors

2021-187 Post-Process Testing Station for Semiconductor Device Fabrication

Published: 7/19/2023 | Inventor(s): Subramanian Iyer, Subramanian Iyer

Keywords(s):

Category(s): Electrical > Sensors, Electrical > Electronics & Semiconductors

2021-167 Non-Volatile SRAM Using Charge Trap Transistors

SUMMARYUCLA researchers in the Department of Electrical and Computer Engineering have developed a fast embedded memory using a standard CMOS logic process that can retain data when the powered down for any reason.BACKGROUNDIn traditional static random-access memory (SRAM), data can be lost when the power supply falls below a certain voltage level. To...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s):

Category(s): Electrical > Electronics & Semiconductors > Memory

2020-770 Apparatus and Method for Changing the Functionality of an Integrated Circuit Using Charge Trap Transistors

SUMMARYUCLA researchers in the Department of Electrical and Computer Engineering have developed a method to overcome manufacturing defects in semiconducting wafers through post-production calibration of integrated circuits by threshold voltage tuning using charge trap transistors. BACKGROUNDComplementary metal-oxide-semiconductors (CMOS) are utilized...

Published: 11/1/2024 | Inventor(s): Subramanian Iyer

Keywords(s):

Category(s): Electrical > Electronics & Semiconductors, Mechanical > Manufacturing, Chemical, Materials > Fabrication Technologies

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