Summary:
UCLA researchers in the department of Electrical and Computer Engineering have developed an on-chip clock propagation circuit that allows creation of large-scale fault-robust processor systems which are essential for the next generation of big data solutions.
Background:
Waferscale processor systems can provide the large number of cores, and interconnect bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive high bandwidth interconnect substrate technology such as silicon interconnect fabric or integrated fan-out system-on-wafer (InFO-SoW). These technologies allow heterogeneous integration where chiplets with different functionalities (e.g., processor, memory) as well as built in disparate technologies (e.g., CMOS and DRAM) can be tightly integrated for significant performance and cost benefits. However, designing large scale systems using these technologies is challenging. One of the most important challenges that needs to be addressed is how to reliably deliver and distribute clock to the chiplets in the system. Existing approaches like the use of crystal oscillators have difficulty generating the load needed to provide clock to a large board and are forced to work at slow oscillations.
Innovation:
Researchers at UCLA have developed an on-chip fast clock which can be integrated into each chiplet. By doing this, the fast clock can be propagated from one chiplet to another. This provides consistent clock signaling to large systems as well as adding redundancy. When individual chiplets fail, additional neighbors can be used to bypass, ensuring that the clock is provided to each chiplet. These self-propagating clocks will allow the creation of even larger processor systems that work more efficiently than off chip clock solutions.
Potential Applications:
• Computer circuitry
• Waferscale computing
• Large-scale processor systems
• Computer clock
• Microprocessor clock
Advantages:
• Scalable to large processor systems
• More efficient than off chip solutions
• Robust to individual chiplet failure
Development to Date:
A successful demonstration of the technology has been made.
Reference: UCLA Case No. 2022-051