Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel manufacturing process for Silicone-Interconnect Fabric (Si-IF) that is not only scalable, but also robust as it relies on established processing techniques from CMOS technologies.
Background:
With the rise of computation-heavy applications, such as machine learning algorithms and neural networks, decreasing the size and improving scalability of packaging technology is critical to enable these applications to exist in small-scale electronic devices. However, printed circuit board (PCB) manufacturing can be tedious, expensive, and inefficient due to the complexity of the processes. While many processes may be automated, the package size of PCBs is often not ideal for increasingly compact devices. In order to meet the demand of ever-increasing machine learning computational power, there is a strong need for a replacement process for PCBs that integrates systems on a single packaging hierarchy.
Innovation:
Silicon Interconnect Fabric (Si-IF) has been developed by researchers at UCLA to replace conventional PCBs and enable a simplified design on a single packaging hierarchy. This scalable technology encompasses packaging substrate fabrication, fine-pitch assembly processes, and high-bandwidth communication interface protocols. The Si-IF technology consists of a silicone-based substrate with complementary metal-oxide semiconductor (CMOS) back-end-of-the-line (BEOL) wiring levels and is terminated with copper pillars so that the Si-IF technology can integrate heterogenous systems to match System-on-chip (SoC) interconnect density. Si-IF technology is robust from a fabrication standpoint as it leverages established techniques and processes that were originally developed for mature CMOS technologies.
Potential Applications:
• Heterogeneous Integration
• IC Packaging
Advantages:
• Scalable
• Relies on established processing protocols
• Encompasses packaging substrate fabrication
• Accommodates high-bandwidth communication interface protocols
• Can match SoC interconnect density
Development to Date:
Invention was reduced to practice in a laboratory setting. Processes have been developed, refined, and implemented on various systems.
Reference: UCLA Case No. 2021-229