Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a shift-trim double-patterning lithography (ST-DPL) technique to improve the manufacturing of microprocessors and allow for densely-featured patterns.
Background:
Photolithography is a common method used for the production of various electrical materials such as microprocessors and integrated circuit boards. This technique utilizes light to fabricate nanoscale patterns and marks on a small surface such as that of a microchip. A photomask is applied over the surface of the microchip to allow the light to generate specific patterns that are often highly-advanced and fine-detailed. The demand for smaller processors has continued to increase, leading manufacturers to approach sub-7nm and even sub-5nm precision features. As these feature sizes shrink, it has become increasingly challenging to densely print using a single photomask, leading chip producers to seek alternative methods. Of these, double-patterning lithography (DPL) has been sought after, however, it is a highly expensive and labor-intensive process. Therefore, there is a need for a technique that allows semiconductor manufacturers to cost-effectively and efficiently produce microprocessors with fine detail.
Innovation:
UCLA researchers led by Professor Puneet Gupta propose shift-trim double-patterning lithography (ST-DPL). This cost-effective method allows manufacturers to double-pattern features using a single photomask. This technique reuses the original mask for the second exposure, allowing manufacturers many benefits over standard pitch-split double patterning. These benefits include reducing mask-cost to nearly half, reduction of overlay errors between the two patterns, alleviating the bimodal line-width distribution problem in double patterning and enhancing the throughput of critical-layer scanners. The proposed method would greatly improve the manufacturing process of semiconducting materials and allow for finer-pitch details.
Potential Applications:
• High-density semiconductor fabrication
• Integrated circuit board manufacturing
• GPU manufacturing
Advantages:
• 50% cost savings versus standard DPL techniques
• Reduces overlay errors between patterns
• Enhances throughput of first-rate scanners
• Saves time on manufacturing process
Development to Date:
Invention has been successfully demonstrated.
Related Publications:
R. S. Ghaida, G. Torres and P. Gupta, "Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control," in IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 1, pp. 93-103, Feb. 2011, doi: 10.1109/TSM.2010.2076305.
Reference:
UCLA Case No. 2010-241
Lead Inventor:
Puneet Gupta