Liquid Metal Printing Technique via Optical Maskless Lithography (Case No. 2024-031)
A research team led by Professor Ximin He has developed a facile and scalable fabrication strategy to make soft electronics using LM particles. By using a photo-reactive ink containing LM particles and a polymer precursor, the team can precisely layer conductive surfaces onto stretchable materials. The researchers demonstrate a resolution of 20 µm and a maximum electrical conductivity of 3×106 S m-1. The fabrication process is performed at room temperature with a simple light exposure, drastically reducing manufacturing costs. This system has been demonstrated for multiple wearable sensors, including gesture monitoring, thermal therapy delivery, and humidity monitoring. Widespread adoption of this technology could greatly advance adoption of soft electronic systems. This liquid metal printing technique is a fast, scalable, nozzle-free, photo-induced, parallel direct printing process, which avoids the drawbacks of other liquid metal printing techniques. It offers the capability of fabricating flexible and stretchable LM-polymer patterns with high resolution, high electrical conductivity, high stretchability and excellent electromechanical stability, in mild manufacturing conditions, using simple commercially available optical maskless lithography with low energy input and short processing time.
Potential Applications:
• Rapid prototyping and manufacturing
• Wearable electronics
• Flexible electronics
• Soft robotics
• Brain-machine interface
Advantages:
• Ambient temperature operation
• Low-cost optical instrumentation
• High electrical conductivity
• High stretchability and electromechanical stability
Related Papers: Fast and Facile Liquid Metal Printing via Projection Lithography for Highly Stretchable Electronic Circuits, Advanced Materials, D. Wu, et al. 2023. https://doi.org/10.1002/adma.202307632
Silicon Interconnect Fabric (Si-IF) Technologies - Subramanian Iyer
A High Throughput Thermal Compression Bonding Scheme for Interposer and Wafer-Scale Advanced Packaging Constructs (Case No. 2023-144)
Under the guidance of Professor Subramanian Iyer, a team of researchers has developed an innovative methodology to enhance throughput for face-to-face heterogeneous dielet bonding. This invention employs a 2-stage bonding approach, combining dielet tacking and assembly-level annealing. The optimization of the tacking stage has resulted in a tacking time within 10 seconds per dielet, and the proposed approach has the capability to increase overall throughput by over 10X to more up to 1100 units-per-hour. Additionally, it ensures military standard mechanical and electrical reliability. Notably, the methodology does not distinguish between die/dielets and can be scaled to accommodate any silicon-interposer, regardless of size. Furthermore, a 2-stage high-throughput thermal compression bonding has been successfully demonstrated using a wafer-scale advanced packaging substrate and was extended to another silicon-interposers, irrespective of the size. This innovative approach holds significant promise for advancing semiconductor packaging capabilities, ushering in a new era of high-throughput, reliable bonding processes.
Potential Applications:
• Advanced packaging constructs
• Dielet assembly on interposers
• Wafer-scale packaging
• High-performance computing applications
Advantages:
• Increase throughput by over 10X, > 1100 units-per-hour
• Tacking optimization within 10 seconds
• Ensure military standard shear strength, high mechanical and electrical reliability
• Flexibility, scales for any silicon-interposer
Processes, Equipment and Materials Recipes, and Related Know-How to Perform the Silicon-Interconnect Fabric (Si-IF) Chip-Scale Packaging Technology (Case No. 2021-229)
With the rise of computation-heavy applications, such as machine learning algorithms and neural networks, decreasing the size and improving scalability of packaging technology is critical to enable these applications to exist in small-scale electronic devices. However, printed circuit board (PCB) manufacturing can be tedious, expensive, and inefficient due to the complexity of the processes. While many processes may be automated, the package size of PCBs is often not ideal for increasingly compact devices. In order to meet the demand of ever-increasing machine learning computational power, there is a strong need for a replacement process for PCBs that integrates systems on a single packaging hierarchy.
Silicon Interconnect Fabric (Si-IF) has been developed by researchers at UCLA to replace conventional PCBs and enable a simplified design on a single packaging hierarchy. This scalable technology encompasses packaging substrate fabrication, fine-pitch assembly processes, and high-bandwidth communication interface protocols. The Si-IF technology consists of a silicone-based substrate with complementary metal-oxide semiconductor (CMOS) back-end-of-the-line (BEOL) wiring levels and is terminated with copper pillars so that the Si-IF technology can integrate heterogenous systems to match System-on-chip (SoC) interconnect density. Si-IF technology is robust from a fabrication standpoint as it leverages established techniques and processes that were originally developed for mature CMOS technologies.
Potential Applications:
• Heterogeneous Integration
• IC Packaging
Advantages:
• Scalable
• Relies on established processing protocols
• Encompasses packaging substrate fabrication
• Accommodates high-bandwidth communication interface protocols
• Can match SoC interconnect density
Apparatus and Method for Changing the Functionality of an Integrated Circuit Using Charge Trap Transistors (Case No. 2020-770)
Complementary metal-oxide-semiconductors (CMOS) are utilized for the generation of integrated circuits used in devices such as memory chips, microprocessors, and other digital/analog circuits. Miniaturization of CMOS circuits produces smaller transistors which are faster and more power efficient. However, reduction in size often results in fabrication defects which can negatively impact the performance of the resulting chip and significantly reduce production yield. Methods to overcome these defects and calibrate the performance of CMOS wafers post-production are therefore vital to increase yield and decrease cost.
UCLA researchers in the Department of Electrical and Computer Engineering have developed a method to increase CMOS wafer yield through post-production modification. Enhancement in performance is achieved through calibrating the threshold voltage of a transistor by charge trapping. Importantly, this method does not incorporate any additional fabrication steps which are lengthy and costly. Overall, enhanced utility of produced CMOS wafers could result in significant downstream cost reduction of consumer electronics.
Potential Applications:
- Electronics
- Memory devices
- Servers
- Computers and tablets
- Wearable Electronics
Advantages:
- Reduces transistor mismatch electronically in post-fabrication
- Fine tunes circuit parameters in a non-volatile fashion
- Extra fabrication steps are not required
- Higher effective yield of produced CMOS wafers
Photo-induced Metal Printing Technique for Creating Metal Patterns and Structures Under Room Temperature (Case No. 2018-377)
UCLA researchers have developed a high-resolution metal deposition and patterning technique. The silver patterns formed by this technique exhibit high electrical conductivity, comparable to or better than the conductivity of silver printed by laser sintering or thermal annealing. The patterning method operates at room temperature, which avoids damaging low-melting-point components or substrates made from plastics. The printing solution is particle-free and solvent-free, and thus easy to operate and environmentally friendly. This technique can print multiple different metals, as a universal platform with the potential to broaden further. The technique can create 2D patterns or 3D structures on a variety of substrates, including plastics, silicon, and paper. Moreover, the simple setup is commercially scalable, avoids costly optical parts, and uses a lower-energy visible light source (compared with commonly used UV light). Overall, this novel room-temperature, particle-free metal patterning is highly desirable for fabricating electronic devices, including integrated circuits, transistors, and sensors.
Patent:
Methods for photo-induced metal printing (11,639,025)
Potential Applications:
- Integrated circuits
- Transistors
- Sensors
- Flexible electronics
- Electrodes for OLED solar cells
Advantages:
- High electrical conductivity
- Operates at room temperature
- Much faster than ink jet printing
- Diverse substrate capabilities
- Setup is commercially scalable and avoids costly parts
- Very high resolution (3 to 5 micrometers)
- Particle-free and seed-free