Background: Over the past two decades, silicon chips have decreased in size by 1000x, while packages on circuit boards have only shrunk by 4x. This will eventually limit scaling of integrated circuits and subsequent processor performance. A solution is the invention of platforms for packageless integration of heterogeneous dies, such as silicon interconnect fabric (Si-IF), exhibiting significant improvements in thermal and electrical properties. Silicon Interconnect Fabric (Si-IF) is a material placed on a silicon wafer that connects multiple bare dielets, allowing for quicker signaling speeds and improved energy efficiency. This silicon-silicon based material may eventually replace printed circuit boards (PCBs) and offer promise in the field of smaller, wearable electronics which require compact processing units.
https://www.chips.ucla.edu/research/project/4
2020-861 Superconducting Silicon Interconnect Fabric (Superconducting-IF)
Background: Quantum computing is an essential part of next generation heterogeneous computing. The computational unit, quantum bit, is very sensitive to energy loss and noise, especially thermal noise. Although various types of quantum computers exist, superconducting quantum computers are an excellent candidate to reduce the mentioned noise and loss problems. Superconducting quantum computers utilize integration method bumps to adhere superconducting dies to substrates. It is impossible, however, to manipulate the height of the bumps with current integration methods during fabrication when the area of the wetting layer is fixed. This has also limited fabrication of silicon interconnects to above cryogenic and below superconducting temperatures. Therefore, a method that can extend the temperature of interconnects and control the height of integration method bumps during fabrication is needed.
Innovation: Superconducting-IF is a platform that allows heterogeneous integration of dies with controlled bump height on silicon wafers and extends the fabrication of silicon interconnects to cryogenic and superconducting temperature ranges. The platform has been successfully prototyped and demonstrated to achieve 10 μm interconnect pitches. The Si-IF is an advanced packaging technology that possesses fine-pitch (≤10 𝜇𝑚), metal-to-metal bonding, high bandwidth, and low latency characteristics. The platform also has low power generation and low power dissipation and also extends the ability to integrate bumps above cryogenic and below superconducting temperature ranges.
Related Materials: Yu-Tao Yang et al., “Demonstration of Superconducting Interconnects on the Silicon Interconnect Fabric Using Thermocompression Bonding,” IEEE 70th Electronic Components and Technology Conference (ECTC), Jun 1-30, 2020, Vista, FL.
STATE-OF-DEVELOPMENT
Development to Date: Platform has been successful prototyped and reduced to practice.
2018-220 Network On Interconnect Fabric
Background: Modern systems contain a variety of heterogeneous circuit blocks, and require ultra large-scale integration to accommodate different applications. Ideally, silicon interconnect fabric (Si-IF) is a compatible platform to satisfy the needs of modern systems through supporting integration of bare (unpackaged) dies using thermal compression bonding on a Si wafer substrate. Fine pitch horizontal and vertical interconnects are feasible within the Si-IF using standard Si processing techniques. However, to enable the Si-IF as a practical platform for ultra large-scale heterogeneous integration, system-level issues, similar to a large system on a chip, must be addressed.
Innovation: Researchers at UCLA have developed a novel network on interconnect fabric (NoIF), which enables integration of ultra large-scale heterogeneous systems within the technologically mature Si-IF platforms. NoIF is based on utility dies that serve as intelligent nodes within the network.
Potential Applications: NoIF offers a wafer-level framework to enable multiple services, including:
- Global and semi-global communication
- Power delivery
- Conversion
- Management, synchronization, testing
Advantages:
- Heterogeneous, ultra large-scale integration
Related Materials:
2018-337 Power Distribution within Silicon Interconnect Fabric
Innovation: Professor Iyer and coworkers have developed a novel method of powering silicon interconnect fabric (Si-IF), a novel platform for heterogeneous systems integration. In this approach, a series of copper stubs are used to connect the back of the Si-IF to the socket. The front of the Si-IF is then powered using through wafer vias (TWVs), which penetrate the silicon substrate. This proposed network demonstrated a voltage drop of 298 µV (distributed voltage of 12V), can distribute multiple voltage domains, and only dissipated 248 mW of power.
Applications: Power distribution network for high power systems integrated on silicon interconnect fabric
Advantages:
- Low power dissipation
- Low voltage drop
- Multiple voltage domains possible
Stage of Development: A silicon interconnect fabric sample with 63,600 mm2 effective area can be powered using this power distribution network. Through wafer vias and copper stub parameters were optimized, resulting in a power distribution network with a voltage drop of 298 µV (distributed voltage of 12V) that supports distribution of multiple voltage domains of 12V and 3.3V, and only dissipated 248 mV of power
Related Materials:
- Saptadeep Pal, D. Petrisko, A. Bajwa, P. Gupta, S. S. Iyer, and R. Kumar "A Case for Packageless Processors", 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 24-28, 2018, Vienna, Austria.
- B. Vaisband, A. Bajwa, and S. S. Iyer, “Network on Interconnect Fabric,” Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2018.
- SivaChandra Jangam, S. Pal, A. Bajwa, S. Parmarti, P. Gupta and S. S. Iyer, "Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme", Proc. of 67th IEEE Electronic Components and Packaging Technology (ECTC) 2017, Orlando, FL, pp. 86-94. doi: 10.1109/ECTC.2017.246
2022-241 A TSV-Less Architecture for Power Delivery and I/O for Interposers and Other Advanced Packaging Constructs
Background: With the rise of machine learning applications, demand for devices capable of high-performance computing (HPC) has also increased. Popularity and demand for wafer-scale engines has grown steadily, serving as a potential solution to this dilemma. Silicon Interconnect Fabric (Si-IF) has been developed by researchers at UCLA in order to enable wafer-scale processing and dense integration of heterogenous dielet-silicon interactions to drastically improve processing power. These wafer-scale systems typically utilize through-silicon vias (TSVs) to supply power and communication to the system. However, manufacturing large wafer-scale systems with TSVs is expensive and complex, and uniform power and signal distribution not guaranteed.
Innovation: UCLA researchers have developed an alternative solution to drilling TSVs that is cheaper, simpler to fabricate, and enables fine-pitch power and signal processing. This solution is a vertical connection by through-polymer-vias (TPVs) located between dielets, enabling signals and power to be routed around, between and under dies to enable uniform delivery. This solution is not limited to Si-IF-based engines and is proposed to improve upon processor designs in general.
Potential Applications:
- Wafer-scale engine design
- High-performance computer design
Advantages:
- Improves processing capabilities
- Affordable and simple manufacturing vs. standard TSVs
- Enables heterogenous integration of microchips
- Improves power and signal communication
Related Materials: H. Ren, S. Pal, G. Ouyang, R. Irwin, Y. -T. Yang and S. S. Iyer, "TSV-less Power Delivery for Wafer-scale Assemblies and Interposers," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022, pp. 1934-1939, doi: 10.1109/ECTC51906.2022.00303.
2021-229 Processes, Equipment and Materials Recipes, and Related Know-How to Perform the Silicon-Interconnect Fabric (Si-IF) Chip-Scale Packaging Technology
UCLA researchers led by Professor Iyer have developed a system to manufacture Silicon-Interconnect Fabric (Si-IF) for wafer-scale engine design. The inventors propose Si-IF as a potential replacement for printed circuit boards (PCBs) because of its numerous advantages, including cost-effectiveness, simplified design on a single packaging hierarchy, and ability to integrate with mature complementary metal-oxide semiconductor (CMOS) technology. The novel Si-IF assembly allows for agnostic dielet structuring and therefore heterogenous integration. The design of the Si-IF provides a platform to integrate a wafer-scale system constituted of a diverse array of dies, enabling high-performance computing. This innovation encompasses the entire fabrication and assembly process of the Si-IF and the assembly of functional dielets. UCLA researchers validated the characteristics and performance benefits of the fine-pitch integration on the Si-IF.