Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel on-chip link that enhances communication performance and energy efficiency in modern integrated circuits.
Background:
On-chip communication enables data transfer between microchip components and is critical in computing, automotive, and industrial control applications. Non-Return-to-Zero (NRZ) signaling offers energy-efficient communication; however, wire delay scales quadratically with length, leading to signal latency. As NRZ links extend, increased bandwidth demands necessitate equalization to mitigate delayed effects. Multilevel signaling is another approach, but this solution often requires excessively wide transmission lines, limiting its practicality on-chip. Thus, there is an unmet need for an on-chip communication link that is energy efficient, scalable over long distances, and capable of supporting high bandwidth needs.
Innovation:
Professor Sudhakar Pamarti and his research team have developed an on-chip multi-level buffered link that significantly improves power efficiency, bandwidth, and data transmission speed. Operating at 9 Gb/s with 76.1 fJ/bit/mm energy efficiency over an 8mm link length in a 22 nm FinFET process, the link maintains a low bit error rate suitable for reliable on-chip communication. The use of thin wires and long links eliminates quadratic wire delay dependence, enabling scalable, high-performance data transfer. The proposed invention addresses impactful communication demands in smartphones, embedded systems, and high-performance computing. By overcoming traditional limitations in chip-to-chip communication, this scalable solution opens new opportunities for improved product performance.
Potential Applications:
● Smartphones, wearables, and IoT devices
● Embedded and industrial control systems
● High-performance computing
● Artificial intelligence accelerators and data-intensive processors
● System-on-Chip architectures and automotive electronics
● Automotive controls
Advantages:
● Low energy per bit
● High bandwidth utilization
● Long-range, efficient data transmission
● Simplified circuit implementation
● Scalable for varying link lengths and applications
State of Development:
First complete description 01/17/24, prototype built and experimentally validated with successful performance outcomes.
Reference:
UCLA Case No. 2025-284
Lead Inventor:
Sudhakar Pamarti