Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a scalable, energy-efficient technique for high-precision threshold voltage tuning and verification in charge trap transistor arrays using low-overhead on-chip measurement.
Background:
Charge trap transistors (CTTs) enable non-volatile analog multi-bit storage through fine tuning of their threshold voltage (VTH), making them attractive for high-density memory, compute in-memory accelerators, and compact data converter arrays. However, accurately programming and verifying precise VTH levels requires high-resolution analog-to-digital converters (ADCs), which introduces significant area and power overhead, especially when scaling to large arrays. Off-chip ADC solutions reduce on-chip complexity but suffer from high energy consumption and slow measurement times (on the order of milliseconds per device), limiting the scalability and practicality of CTT-based systems. Thus, there remains an unmet need for a fast, energy-efficient and scalable method to accurately measure and verify VTH in large CTT arrays.
Innovation:
Professor Sudhakar Pamarti and his research team have developed a VTH measurement and calibration technique that utilizes a coarse on-chip ADC combined with multiple fast sequential measurements to achieve high effective precision with low overhead. The method enables accurate programming of large-scale CTT arrays while minimizing area and power consumption. Experimental validation on 255 CTTs within an 8-bit DAC demonstrates calibration to full 8-bit accuracy, achieving around 37 times reduction in mismatch variation and low linearity error (0.87/1.75 LSB DNL/INL). This approach eliminates the need for complex circuit-level calibration and supports the use of near-minimum-sized transistors as current sources, improving density and scalability in advanced CMOS nodes. Additionally, the research team has furthered this work with on-chip programming of CTTs using standard CMOS processes, enabling precise, reversible, and non-volatile VTH tuning via programmable voltage pulses. Together, these innovations enable fast, scalable, and energy-efficient programming and verification of CTT arrays, significantly advancing their viability for high-density memory and compute-in-memory applications.
Potential Applications:
● CMOS memory (non-volatile multi-bit storage)
● Compute-in-memory accelerators (AI/ML hardware)
● High-density DAC/ADC arrays
● Edge AI and low-power embedded systems
● Reconfigurable analog/mixed-signal circuits
Advantages:
● High-precision VTH tuning with low-resolution ADC
● Reduced power and area overhead
● Eliminates need for complex calibration circuitry
● Improved device matching and linearity
● Enables high-density and energy-efficient designs
Status of Development:
First successful demonstration completed July 2024.
Related Publications:
1. M. Zeinali and S. Pamarti, “A Compact 8b Thermometer CTT DAC with On-Chip Calibration Circuits,” IEEE Solid-State Circuits Lett., submitted for publication.
2. M. Zeinali and S. Pamarti, "On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC," in IEEE Solid-State Circuits Letters, vol. 9, pp. 53-56, 2026, doi: 10.1109/LSSC.2026.3656261.
Reference:
UCLA Case No. 2026-167
Lead Inventors:
Sudhaka Pamarti, Faculty, Department of Electrical and Computer Engineering
Mohammadreza Zeinali, Ph.D. Student, Department of Electrical Engineering