2022-051 Reliable and Fault-Tolerant Clock Generation and Distribution for Chiplet-Based Waferscale Processors
Researchers at UCLA have developed an on-chip fast clock which can be integrated into each chiplet. By doing this, the fast clock can be propagated from one chiplet to another. This provides consistent clock signaling to large systems as well as adding redundancy. When individual chiplets fail, additional neighbors can be used to bypass, ensuring that the clock is provided to each chiplet. These self-propagating clocks will allow the creation of even larger processor systems that work more efficiently than off chip clock solutions.
2021-400 COMET: On-Die and In-Controller Collaborative Memory ECC Technique for Stronger and Safer Correction of DRAM Errors
To solve this issue, UCLA researchers in the Department of Electrical and Computer Engineering have developed Collaborative Memory ECC Technique (COMET). This method efficiently co-designs two of the error correcting coding (ECC) codes to guarantee no silent data corruption when a double-bit error happens within the dynamic random-access memory (DRAM). Moreover, the method allows the collaboration between the on-die and in-controller ECC decoders that corrects most of the double-bit errors without adding any more redundancy bits to either of the two codes. Furthermore, COMET was able to eliminate all double-bit error induced silent data corruptions and corrected ~99.9997% of double bit errors with negligible data, power, and performance impact. COMET can be implemented by manufacturers to improve the overall performance of DRAM components and ultimately reduce data storage and transmission errors.
2016-684 Resistive Memory Write and Read Assistance using Negative Differential Resistance Device
UCLA researchers proposed a new memory read and write circuitry that can solve all the three problems above. This new design uses negative differential resistance (NDR) devices in series with the memory cell write or read current path. The use of pre-charge transistor and pre-charge pulse sequence is employed to maximize the usefulness of the NDR device. A NDR can also be shared and connected to the several bit-lines that share a sense amplifier.
2021-212 Configurable Memory Pool System
UCLA researchers in the Department of Electrical and Computer Engineering have developed a densely integrated, chiplet based networked memory pool with high intra-pool bandwidth. The chiplet architecture provides a common interface to the network, allowing the memory to be assembled in a variety of different configurations. This allows for different memory interfaces such as DDRx/LPDDRx/GDDRx/PCle and communication interfaces such as OMI, Gen-Z, & CXL to be compatible without modifying the rest of the system. The memory pool can be scaled in capacity, and downstream interconnection of heterogenous technologies can be achieved. The developed processing node architecture could allow novel processing designs to be achieved.
2010-241 Single-Mask Double-Patterning Lithography
Photolithography is a common method used for the production of various electrical materials, such as microprocessors and integrated circuit boards. This technique utilizes light to fabricate nanoscale patterns and marks on a small surface such as that of a microchip. As manufacturers approach sub-5nm precision, it has become increasingly challenging to densely print features on a single photomask. Prof. Gupta and team propose shift-trim double-patterning lithography (ST-DPL), a cost-effective method allowing manufacturers to double-pattern a single photomask. This technique reuses the original mask for the second exposure, allowing manufacturers many benefits over standard pitch-split double patterning. These benefits include reducing mask-cost to nearly half, reduces overlay errors between the two patterns, alleviating the bimodal line-width distribution problem in double patterning and slightly enhancing the throughput of critical-layer scanners.