Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a transistor-level method that dynamically tunes device characteristics to eliminate mismatch, achieving higher stability and precision without added area or power costs.
Background:
Transistors are the fundamental semiconductor building blocks for amplification, switching, and a wide range of digital processing and signal modulation applications. However, they are inherently subject to device-to-device mismatch and parametric variation due to process variability at the nanoscale. In many analog, mixed-signal, and RF circuits, precise device matching is essential for maintaining linearity, minimizing offset, and achieving optimal system performance. Fabrication defects further exacerbate these issues, leading to degraded performance, reduced yield, and the need for extra area or circuit-level compensation. Current approaches to mitigate mismatch include device sizing, common-centroid layout techniques, trimming, and digital calibration. While these approaches may reduce variability, they often introduce large demands in area, power, or complexity. There remains an unmet need for a method to intrinsically suppress mismatch effects, providing stable device characteristics without heavy reliance on external compensation or elaborate design techniques.
Innovation:
Professor Subu Iyer and his research team have developed a novel transistor-level method to substantially reduce circuit mismatch without incurring additional cost in area and power. Experimental results demonstrate a reduction in voltage-voltage mismatch by at least 100 mV, along with an expanded programmable threshold voltage dynamic range. The use of fully-depleted silicon-on-insulator (FD-SOI) transistors allows for increased electrostatic control of both the front gate and back gate of the transistor by coordinated modulation. By dynamically tuning the effective threshold voltage, mismatch can be suppressed at its source. Parameters such as leakage current and drive current can be adaptively adjusted such that unique variability cases inherent in semiconductor fabrication can be resolved. This capability represents a significant advancement, offering a pathway to greater stability, precision, and design flexibility in advanced circuit architectures.
Potential Applications:
- Analog and mixed-signal circuits
- RF front-ends and transceivers
- Precision amplifiers and data converters
- Low-power IoT devices
- High-speed digital logic
Advantages:
- Significant mismatch reduction
- Wider threshold voltage range
- Greater design flexibility
- Enhanced stability and precision
- No area or power costs
Status of Development:
First successful demonstration of the invention: December 2024.
Related Publications:
- Xuefeng Gu & S. S. Iyer, “Fine-grained analog memory device based on charge-trapping in high-K gate dielectrics of transistors,” https://patents.google.com/patent/US10585643B2. (Granted 2020).
- Frank Chang et al, “Memristive neural network computing engine using cmos-compatible charge-trap-transistor (ctt),” https://patents.google.com/patent/WO2019100036A1/. (Published 2019)
- Steven Moran, et. al, “Neural network system with neurons including charge-trap transistors and neural integrators and methods therefore”. (Submitted 2021).
Reference:
UCLA Case No. 2025-271
Lead Inventor:
Subu Iyer, Distinguished Professor & Charles P. Reames Endowed Chair, Department of Electrical and Computer Engineering