Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a liquid-metal-based, nondestructive probing platform for high-density semiconductor die and assembly testing.
Background:
As semiconductor devices become smaller and more complex, manufacturers face growing challenges in testing chips before they are assembled into advanced packages. Modern chips use extremely small, closely spaced input/output (I/O) pads, making reliable electrical testing at the wafer stage increasingly difficult. Traditional probe technologies require large, dedicated test pads to contact the chip. To accommodate this, designers must add extra structures that consume valuable silicon area, complicate routing, and increase manufacturing cost. These tradeoffs directly impact yield, performance, and overall economics. The challenge is even more critical for multi-die and heterogeneous packages, where multiple chips are integrated into a single high-value module. These systems are expensive to build, cannot be reworked once assembled, and are highly sensitive to defective components. As a result, manufacturers must ensure that only “Known Good Die” (KGD) move forward to assembly. However, existing test approaches can introduce mechanical or electrical stress that risks damaging the die or limiting test accuracy. There is a clear need for a more efficient probing solution—one that enables reliable, fine-pitch electrical access without damaging the chip, while reducing design overhead and simplifying the path to Known Good Die qualification.
Innovation:
To address these limitations, Professor Subu Iyer and his research group have developed a novel liquid-metal probe architecture that enables nondestructive electrical testing of fine-pitch semiconductor dies and assembled devices. The system supports pad pitches below 100 micrometers and into the submicron range by using a conductive liquid interface that eliminates rigid mechanical contact, minimizing stress and preserving surface integrity. A multilayer, high-fanout fabrication process allows dense routing from small pads to standard test hardware, while liquid-metal confinement prevents residue and cross-contamination. The resulting plug-and-play, reconfigurable platform allows chiplets, MEMS, and sensitive devices to be hot-swapped and tested prior to final assembly. This approach significantly improves KGD qualification and reduces yield loss and assembly risk in advanced semiconductor packaging. Together, these capabilities establish a scalable and manufacturing-compatible test solution that lowers cost, improves yield, and enables the next generation of high-density semiconductor integration.
Potential Applications:
● Known Good Die testing
● Advanced packaging and chiplet integration
● Wafer-level probing of fine-pitch I/O
● MEMS and sensor device testing
● Biocompatible and soft electronic interfaces
Advantages:
● Nondestructive, low-stress electrical probing
● Supports ultra-fine pad pitches
● High fan-out, multilayer interconnect capability
● Preserves surface integrity and yield
State of Development:
First description of complete invention: March 2025
Related Publications:
1. Kim, Mg., Brown, D.K. & Brand, O. Nanofabrication for all-soft and high-density electronic devices based on liquid metal. Nat Commun 11, 1002 (2020). https://doi.org/10.1038/s41467-020-14814-yK.
2. Amponsah and A. Lal, "Multiple tip nano probe actuators with integrated JFETs," 2012 IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS), Paris, France, 2012, pp. 1356-1359, doi: 10.1109/MEMSYS.2012.6170418.
Reference:
UCLA Case No. 2026-073
Lead Inventor:
Subu Iyer, Distinguished Professor, Department of Electrical and Computer Engineering