Summary:
UCLA researchers in the Department of Electrical and Computer Engineering have developed a transformer-based, high-density power delivery architecture that enables efficient, scalable, and low-loss energy distribution for next-generation wafer-scale and chiplet-based systems.
Background:
Chiplet-based and wafer-scale integrated systems demand increasingly high power levels, requiring dense and efficient power delivery networks to minimize losses and support scaling. However, conventional approaches, such as buck and switched-capacitor converters are limited in achievable efficiency and power density, while also introducing challenges in thermal management and noise coupling. These limitations become more pronounced at wafer scale, where power delivery must support large-area integration and high compute density. As next-generation applications in artificial intelligence and high-performance computing continue to scale, existing power delivery solutions present a fundamental bottleneck in efficiency, scalability, and integration. Thus, there remains an unmet need for a high-efficiency, high-density power delivery architecture tailored for wafer-scale and chiplet-based systems.
Innovation:
To address these limitations, Professor Subu Iyer and his research team have developed a high-efficiency power delivery architecture using substrate- and wafer-level integrated transformer arrays for chiplet-based systems. The design employs high turns-ratio (at least 48:1) transformers with high-permeability magnetic materials to enable efficient high-voltage AC distribution and direct AC-to-AC conversion. The system achieves above 90% efficiency and over 1 W/mm2 power density, outperforming conventional approaches. The use of embedded transformer arrays enables direct integration within silicon interconnect fabrics (Si-IF), supporting compact and scalable implementation. This architecture enables scalable, low-loss delivery of multi-kilowatt power on a single wafer, addressing a key bottleneck for next-generation AI and high-performance computing systems.
Potential Applications:
● Large-scale AI/HPC power delivery networks
● Wafer-scale integrated systems
● Advanced semiconductor fabrication processes
● Embedded transformer-based power architectures
● High-density chiplet-based platforms
Advantages:
● High power density ( >1 W/mm2) with >90% efficiency
● Direct, localized point-of-load conversion
● Reduced IR drop and parasitic losses
● Scalable to multi-kW wafer-level systems
● Efficient high-voltage AC power distribution
State of Development:
First successful demonstration in process.
Related Publications:
1. S. S. Iyer, S. Jangam and B. Vaisband, "Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems," in IBM Journal of Research and Development, vol. 63, no. 6, pp. 5:1-5:16, 1 Nov.-Dec. 2019, doi: 10.1147/JRD.2019.2940427.
2. S. Jangam and S. S. Iyer, "Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 5, pp. 727-738, May 2021, doi: 10.1109/TCPMT.2021.3075219.
Reference:
UCLA Case No. 2026-075
Lead Inventor:
Professor Subramanian Iyer