Search Results - latency+(engineering)

1 Results

Sort By:

2021-212 Configurable Memory Pool System

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a node processing architecture that allows memory pool to be scalable and allows the integration of heterogeneous technologies downstream. Background: Modern electronic applications require high memory capacity and bandwidth. However, many of these applications...

Published: 12/22/2023 | Inventor(s): Puneet Gupta, Saptadeep Pal, Matthew Tomei, Rakesh Kumar

Keywords(s): Bandwidth (Computing), Dynamic Random-Access Memory, Electrical Engineering, Flash Memory, Latency (Engineering), Magnetoresistive Random-Access Memory, Random-Access Memory, Static Random-Access Memory

Category(s): Electrical, Electrical > Electronics & Semiconductors > Circuits, Electrical > Electronics & Semiconductors