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2021-229 Processes, Equipment and Materials Recipes, and Related Know-How to Perform the Silicon-Interconnect Fabric (Si-IF) Chip-Scale Packaging Technology

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel manufacturing process for Silicone-Interconnect Fabric (Si-IF) that is not only scalable, but also robust as it relies on established processing techniques from CMOS technologies. Background: With the rise of computation-heavy applications, such...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Analogue Electronics, CMOS, Consumer Electronics, Digital Electronics, Electronic Packaging, Electronics & Semiconductors, electronics packaging, heterogenous electronic systems, Integrated Circuit Via (Electronics), Interposers, Nanotechnology, Power Electronics, Printed Circuit Board, Printed Electronics, Silicon

Category(s): Electrical, Electrical > Electronics & Semiconductors, Materials, Materials > Nanotechnology, Electrical > Electronics & Semiconductors > Memory