Search Results - low-density+parity-check+code

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2022-023 COPYRIGHT: FIELD-PROGRAMMABLE GATE ARRAY (FPGA) CORE FOR PROTOGRAPH-BASED RAPTOR-LIKE (PBRL) LOW-DENSITY PARITY-CHECK (LDPC) ENCODING AND DECODING

SUMMARY: UCLA researchers in the Department of Electrical and Computer Engineering have developed a software that serves as field programmable gate arrays (FPGAs) encoder and decoder for optical communications. BACKGROUND: Satellite communications requires wireless communication techniques that are resilient, secure, and able to process high volumes...

Published: 11/15/2024 | Inventor(s): Richard Wesel, Linfang Wang, Dariush Divsalar, Caleb Terill, Chester Hulse, Sean Chen, Calvin Kuo

Keywords(s): Aerospace Engineering, Communications Satellite, Field-Programmable Gate Array, Low-Density Parity-Check Code, Telecommunication, Wireless

Category(s): Software & Algorithms, Software & Algorithms > Communication & Networking, Electrical, Electrical > Wireless, Software & Algorithms > Programs

LDPC Minsum Decoder With Neural-Network-Optimized Degree-Specific Weights (Case No. 2021-239)

SUMMARY: UCLA researchers in the Department of Electrical and Computer Engineering have developed a neural network-based approach to decode Low Density Parity Codes (LDPCs) that is capable of accurately transmitting large bit number data faster and with a lower frame rate error that conventional approaches. BACKGROUND: The transmission of data at...

Published: 11/15/2024 | Inventor(s): Richard Wesel, Linfang Wang, Sean Chen, Dariush Divsalar, Jonathan Nguyen

Keywords(s): Algorithm, Artificial Neural Network, Data Recovery, Error Detection And Correction, Information Theory, Low-Density Parity-Check Code, Parity-Check Matrix, Software & Algorithms, Telecommunication

Category(s): Software & Algorithms > Communication & Networking, Software & Algorithms, Electrical > Signal Processing, Software & Algorithms > Artificial Intelligence & Machine Learning, Electrical > Wireless, Software & Algorithms > Programs