Summary:
UCLA researchers led by Professor Iyer have developed a wafer-scale processor manufacturing method that does not require standard through-silicon vias (TSVs).
Background:
With the rise of machine learning applications, demand for devices capable of high-performance computing (HPC) has also increased. Popularity and demand for wafer-scale engines has grown steadily, serving as a potential solution to this dilemma. Silicon Interconnect Fabric (Si-IF) has been developed by researchers at UCLA in order to enable wafer-scale processing and dense integration of heterogenous dielet-silicon interactions to drastically improve processing power. These wafer-scale systems typically utilize through-silicon vias (TSVs) to supply power and communication to the system. However, manufacturing large wafer-scale systems with TSVs is expensive and complex, and uniform power and signal distribution not guaranteed.
Innovation:
UCLA researchers have developed an alternative solution to drilling TSVs that is cheaper, simpler to fabricate, and enables fine-pitch power and signal processing. This solution is a vertical connection by through-polymer-vias (TPVs) located between dielets, enabling signals and power to be routed around, between and under dies to enable uniform delivery. This solution is not limited to Si-IF-based engines and is proposed to improve upon processor designs in general.
Potential Applications:
- Wafer-scale engine design
- High-performance computer design
Advantages:
- Improves processing capabilities
- Affordable and simple manufacturing vs. standard TSVs
- Enables heterogenous integration of microchips
- Improves power and signal communication
Related Publications:
H. Ren, S. Pal, G. Ouyang, R. Irwin, Y. -T. Yang and S. S. Iyer, "TSV-less Power Delivery for Wafer-scale Assemblies and Interposers," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022, pp. 1934-1939, doi: 10.1109/ECTC51906.2022.00303.