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Multi-Level Scheduling and Partitioning of Reconfigurable Processor Arrays (Case No. 2026-011) Circular Elevator Style Network-on-Chip (Case No. 2026-012) and Pattern Compilation for Runtime Reconfigurable Arrays (Case No. 2026-013)

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a high-speed runtime reconfigurable processor array (RTRA) that enables on-chip scheduling and rapid multi-program execution with unprecedented energy and area efficiency for dynamic computing workloads. Background: Dynamic digital signal processing...

Published: 12/11/2025 | Inventor(s): Dejan Markovic, Hong Seok Lee, Chenkai Ling

Keywords(s): computational efficiency, computational efficiency and analysis, edge computing, energy-efficient, Hardware, high speed, large-area arrays, low latency computing, low-power architecture, Microarray, Microprocessor, processor design, programming, scalable manufacturing, System On A Chip

Category(s): Electrical > Signal Processing, Electrical, Electrical > Electronics & Semiconductors, Software & Algorithms, Electrical > Computing Hardware

2009-454 Nano-Plasmonic Lucas: Towards Mega-Throughput, Label-Free Genomics and Proteomics: Revolutionizing Micro-Array Technologies

Revolutionizing Micro-Array Technologies: A Microscopy Method and System Incorporating Nanofeatures Summary: UCLA researchers in the Department of Electrical Engineering have developed a novel lensfree incoherent holographic microscope using a plasmonic aperture. Background: Lensfree imaging has gained interest due to the potential to eliminate...

Published: 2/14/2025 | Inventor(s): Aydogan Ozcan

Keywords(s): Digital Holography, Functional Genomics, Holography, Microarray

Category(s): Electrical, Life Science Research Tools