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Accurate Compute-In-Memory Accelerator With Multi-Level Analog Weight Storage (Case No. 2026-169)

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a high-density, multi-level CTT-based compute-in-memory architecture that enables precise, energy-efficient analog computation directly within memory for high-performance computing. Background: Conventional digital processors for artificial intelligence...

Published: 6/3/2026 | Inventor(s): Sudhakar Pamarti, Mohammadreza Zeinali, Samyak Chakrabarty, Vinod Kurian Jacob

Keywords(s): Advanced Computing / AI, advanced computing methods, AI, AI hardware, analog computing, Artificial Intelligence, artificial intelligence accelerators, Artificial Neural Network, CMOS, compute-in-memory, edge computing, Energy Efficiency, high-performance computing, Memory, parallel computing, Transistor, transistors

Category(s): Software & Algorithms > Artificial Intelligence & Machine Learning, Electrical, Electrical > Computing Hardware, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Circuits, Electrical > Electronics & Semiconductors > Memory