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Efficient Stochastic Compute-In-Memory Circuit for Multi-Level or Accumulation (Case No. 2024-122)
Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel computational hardware that combines stochastic computing with compute-in-memory techniques that improves speed and computational efficiency. Background: In recent years, the need for advanced computational technologies has surged, driven by...
Published: 7/8/2024
|
Inventor(s):
Sudhakar Pamarti
,
Jiyue Yang
,
Soumitra Pal
,
Puneet Gupta
,
Tianmu Li
,
Wojciech Romaszkan
Keywords(s):
computational efficiency
,
Computer Architecture
,
Integrated Circuit
,
Logic Gate
,
neural network
,
Stochastic Computing (SC)
Category(s):
Electrical > Computing Hardware
,
Electrical > Electronics & Semiconductors > Circuits
Charge Trap Transistors - Subramanian Iyer
Background: Due to their chemical makeup and heat generation, devices such as high-k/metal gate (HKMG) CMOS often accumulate charges can lead to variation in integrated circuits. Charge Trap Transistors (CTT's) utilize accumulating charge in semiconducting devices as embedded non-volatile memory (eNVM). The introduction of CTT's can prove an...
Published: 7/19/2023
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Inventor(s):
Subramanian Iyer
Keywords(s):
Charge Carrier
,
CMOS
,
Dynamic Random-Access Memory
,
Electrical
,
Electrical Engineering
,
Electrical Load
,
Electrical Resistance And Conductance
,
Logic Gate
,
Magnetoresistive Random-Access Memory
,
Medical Device
,
Memory
,
Power Electronics
,
Power Transmission
,
Programmable Logic Device
,
Random-Access Memory
,
Resistive Random-Access Memory
,
Semiconductor Device
,
Semiconductor Device Fabrication
,
Static Random-Access Memory
,
Transistor
Category(s):
Electrical
,
Electrical > Electronics & Semiconductors > Memory
,
Electrical > Electronics & Semiconductors