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Stain-Free, Rapid, and Quantitative Viral Plaque Assay Using Deep Learning and Holography (Case No. 2022-326)

Intro Sentence: UCLA researchers in the Department of Electrical and Computer Engineering have developed a rapid and stain-free quantitative assay using lens-free holography and deep learning to efficiently and cost-effectively determine the presence of viral plaque-forming units (PFUs) in samples. Background: A broad range of viruses have caused...

Published: 3/7/2024 | Inventor(s): Aydogan Ozcan, Yuzhu Li, Tairan Liu

Keywords(s): Antiviral Drug, Artifical Intelligence (Machine Learning, Data Mining), Assay, Bioassay, Computer Aided Learning, Diagnostic Markers & Platforms, Diagnostic Platform Technologies (E.G. Microfluidics), Diagnostic Test, Digital Holography, Electrical, Electrical Brain Stimulation, Electrical Breakdown, Electrical Engineering, Electrical Impedance, Electrical Load, Electrical Load Equation Of State, Electrical Resistance And Conductance, Electrical Resistivity And Conductivity, Holography, Immunoassay, Immunoassay Sense (Molecular Biology), Lentivirus Viral Vector, Machine Learning, Machine Learning Autonomous Car Gradient Descent, Machine Learning Pain Management, Machine Learning Particulates Global Climate Model, Network Analysis (Electrical Circuits), Perceptual Learning, Plasmid Trabecular Meshwork Aqueous Humour Viral Vector, Targets And Assays, Transcutaneous Electrical Nerve Stimulation, Transfection Viral Vector, Unsupervised Learning , Viability Assay, Viral Delivery Systems, Viral Envelope, Viral Load

Category(s): Diagnostic Markers, Diagnostic Markers > Targets And Assays, Electrical, Life Science Research Tools, Life Science Research Tools > Research Methods, Life Science Research Tools > Other Reagents, Software & Algorithms > Artificial Intelligence & Machine Learning

2022-241 A TSV-Less Architecture for Power Delivery and I/O for Interposers and Other Advanced Packaging Constructs

Summary: UCLA researchers led by Professor Iyer have developed a wafer-scale processor manufacturing method that does not require standard through-silicon vias (TSVs). Background: With the rise of machine learning applications, demand for devices capable of high-performance computing (HPC) has also increased. Popularity and demand for wafer-scale...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer, Haoxiang Ren, Saptadeep Pal

Keywords(s): Amorphous Silicon, Artifical Intelligence (Machine Learning, Data Mining), Artificial Intelligence, Artificial Neural Network, Bandwidth (Signal Processing), Brain-Computer Interface, Brain-Computer Interface Body Mass Index, Chipset, Clock Signal, Computer Aided Design & Manufacturing, Computer Aided Learning, Computer Architecture, Computer Monitor, Computer Security, Computer Virus, Computer Vision, Computer-Aided Design, Computer-Aided Diagnosis, Continuum Mechanics Computer Graphics Collision Detection, Digital Signal Processing, Doping (Semiconductor), Electrical, Electrical Engineering, Electrical Impedance, Electrical Load, Electrical Resistance And Conductance, Electrical Resistivity And Conductivity, Electronics & Semiconductors, Graphics Processing Unit, Graphics Processing Unit Analog Computer, Human-Computer Interaction, Machine Learning, Machine Vision, Manufacturing, Microelectronics Semiconductor Device Fabrication, Microprocessor, Network Analysis (Electrical Circuits), Network On A Chip, Organic Semiconductor, Quantum Computer, Semiconductor, Semiconductor Device, Semiconductor Device Fabrication, Semiconductor Ohmic Contact, Semiconductor Risk Assessment, Semiconductor Sapphire, Semiconductors, Signal Processing, Silicon, Silicon Dioxide, Silicon Working Electrode Perovskite (Structure), Silicon-Germanium, Supercomputer, System On A Chip, Tablet Computer

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Signal Processing, Materials > Semiconducting Materials, Electrical > Electronics & Semiconductors > Circuits, Software & Algorithms > Artificial Intelligence & Machine Learning

Silicon Interconnect Fabric (Si-IF) Technologies - Subramanian Iyer

Background: Over the past two decades, silicon chips have decreased in size by 1000x, while packages on circuit boards have only shrunk by 4x. This will eventually limit scaling of integrated circuits and subsequent processor performance. A solution is the invention of platforms for packageless integration of heterogeneous dies, such as silicon interconnect...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Amorphous Silicon, Antenna (Radio) Flip Chip DisplayPort, Application-Specific Integrated Circuit, Bandwidth (Signal Processing), Bandwidth (Signal Processing) RF Transmitters, Brain-Computer Interface, Brain-Computer Interface Body Mass Index, Chipset, Computer Aided Design & Manufacturing, Computer Aided Learning, Computer Architecture, Computer Monitor, Computer Security, Computer Virus, Computer Vision, Computer-Aided Design, Computer-Aided Diagnosis, Continuum Mechanics Computer Graphics Collision Detection, Digital Signal Processing, Doping (Semiconductor), Electrical, Electrical Brain Stimulation, Electrical Breakdown, Electrical Engineering, Electrical Impedance, Electrical Load, Electrical Load Equation Of State, Electrical Resistance And Conductance, Electrical Resistivity And Conductivity, Electronics & Semiconductors, Enzyme Substrate (Biology), Graphics Processing Unit, Graphics Processing Unit Analog Computer, Human-Computer Interaction, Image Processing, Integrated Circuit, Integrated Circuit Standing Wave, Integrated Circuit Via (Electronics), Lab-On-A-Chip, Microelectronics Semiconductor Device Fabrication, Microprocessor, Mixed-Signal Integrated Circuit, Monolithic Microwave Integrated Circuit, Network Analysis (Electrical Circuits), Network On A Chip, Organic Semiconductor, Photonic Integrated Circuit, Printed Circuit Board, Process Optimization, Quantum Computer, Semiconductor, Semiconductor Device, Semiconductor Device Fabrication, Semiconductor Ohmic Contact, Semiconductor Risk Assessment, Semiconductor Sapphire, Semiconductors, Short Circuit, Signal Processing, Silicon, Silicon Dioxide, Silicon Working Electrode Perovskite (Structure), Silicon-Germanium, Substrate (Chemistry), Supercomputer, System On A Chip, Tablet Computer, Three-Dimensional Integrated Circuit, Transcutaneous Electrical Nerve Stimulation, zzsemiconducting materials

Category(s): Electrical, Electrical > Electronics & Semiconductors, Materials, Materials > Semiconducting Materials, Medical Devices, Medical Devices > Coatings

Charge Trap Transistors - Subramanian Iyer

Background: Due to their chemical makeup and heat generation, devices such as high-k/metal gate (HKMG) CMOS often accumulate charges can lead to variation in integrated circuits. Charge Trap Transistors (CTT's) utilize accumulating charge in semiconducting devices as embedded non-volatile memory (eNVM). The introduction of CTT's can prove an...

Published: 7/19/2023 | Inventor(s): Subramanian Iyer

Keywords(s): Charge Carrier, CMOS, Dynamic Random-Access Memory, Electrical, Electrical Engineering, Electrical Load, Electrical Resistance And Conductance, Logic Gate, Magnetoresistive Random-Access Memory, Medical Device, Memory, Power Electronics, Power Transmission, Programmable Logic Device, Random-Access Memory, Resistive Random-Access Memory, Semiconductor Device, Semiconductor Device Fabrication, Static Random-Access Memory, Transistor

Category(s): Electrical, Electrical > Electronics & Semiconductors > Memory, Electrical > Electronics & Semiconductors