Search Results - electrical+%3e+electronics+%26+semiconductors

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A Wearable Magnetoelastic Patch for Cervical Spines Care (Case No. 2026-076)

Summary: UCLA researchers have developed a soft, wearable magnetoelastic patch designed for real-time, non-invasive monitoring of cervical spine pressure and motion, enabling early detection and personalized care for infants with potential neck or spine disorders. Background: Infant cervical spine injuries present a significant diagnostic challenge...

Published: 2/4/2026 | Inventor(s): Jun Chen

Keywords(s): Neurosurgery/Spine

Category(s): Diagnostic Markers > Pediatrics, Electrical > Electronics & Semiconductors, Electrical > Flexible Electronics, Electrical > Sensors, Materials > Fabrication Technologies, Mechanical > Sensors, Medical Devices > Monitoring And Recording Systems, Software & Algorithms > AI Algorithms, Therapeutics

A Selenium Buffer Method for Making Van Der Waals Contact on CDTE Wafers With High Surface Roughness (Case No. 2025-173)

Summary: UCLA researchers in the Department of Chemistry & Biochemistry have developed a novel method for implementation of Van der Waals contact on commercial CdTe wafers for improved photovoltaic and solar panel production. Background: Cadmium Telluride (CdTe) is a common absorber used for thin-film optoelectronics and photovoltaics, including...

Published: 1/28/2026 | Inventor(s): Yu Huang, Xiangfeng Duan, Bangyao Hu

Keywords(s):

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Waferscale Computing, Chemical, Chemical > Chemical Processing & Manufacturing, Chemical > Instrumentation & Analysis, Electrical > Sensors, Energy & Environment, Energy & Environment > Energy Efficiency, Energy & Environment > Energy Generation, Materials, Materials > Semiconducting Materials

Multi-Level Scheduling and Partitioning of Reconfigurable Processor Arrays (Case No. 2026-011) Circular Elevator Style Network-on-Chip (Case No. 2026-012) and Pattern Compilation for Runtime Reconfigurable Arrays (Case No. 2026-013)

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a high-speed runtime reconfigurable processor array (RTRA) that enables on-chip scheduling and rapid multi-program execution with unprecedented energy and area efficiency for dynamic computing workloads. Background: Dynamic digital signal processing...

Published: 12/11/2025 | Inventor(s): Dejan Markovic, Hong Seok Lee, Chenkai Ling

Keywords(s): computational efficiency, computational efficiency and analysis, edge computing, energy-efficient, Hardware, high speed, large-area arrays, low latency computing, low-power architecture, Microarray, Microprocessor, processor design, programming, scalable manufacturing, System On A Chip

Category(s): Electrical > Signal Processing, Electrical, Electrical > Electronics & Semiconductors, Software & Algorithms, Electrical > Computing Hardware

CDMA MIMO Readout Networks for Semiconductor-Based Compact 2-Dimensional Qubit Array (Case No. 2025-153)

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel CDMA-MIMO qubit readout network that enables scalable, high-fidelity measurement of two-dimensional semiconductor qubit arrays for fault-tolerant quantum computing. Background: Qubit arrays form the foundation of complex quantum computations...

Published: 12/12/2025 | Inventor(s): Mau-Chung Chang, Jhih-Wei Chen

Keywords(s): computational efficiency, computational efficiency and analysis, Electrical, Electrical Engineering, Electronics & Semiconductors, large-area arrays, quantum communication, Quantum Computer, quantum error correction (QEC), quantum network, quantum processing, quantum processor, Semiconductor, Semiconductor Device, Semiconductors

Category(s): Electrical, Electrical > Computing Hardware, Electrical > Electronics & Semiconductors, Electrical > Quantum Computing, Software & Algorithms > Communication & Networking, Software & Algorithms

Method for Reducing Process Variation-Induced Threshold Voltage Mismatch in FD-SOI Transistors (Case No. 2025-271)

Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a transistor-level method that dynamically tunes device characteristics to eliminate mismatch, achieving higher stability and precision without added area or power costs. Background: Transistors are the fundamental semiconductor building blocks for amplification,...

Published: 10/23/2025 | Inventor(s): Subramanian Iyer, Siyun Qiao, Jacklyn Zhu, Samuel Wang

Keywords(s): device stability, Electronics & Semiconductors, frequency modulation, Integrated Circuit, Integrated Circuit Via (Electronics), Microelectronics Semiconductor Device Fabrication, Mixed-Signal Integrated Circuit, Semiconductor, Semiconductor Device, Semiconductor Device Fabrication, Semiconductors, Signal Processing, Silicon, Transistor, transistors

Category(s): Electrical, Electrical > Signal Processing, Electrical > Instrumentation, Electrical > Electronics & Semiconductors, Software & Algorithms, Software & Algorithms > Communication & Networking

Doping of Thorium-229 Into High Bandgap Metal Sulfate Material (Case No. 2025-99Y)

Summary: A UCLA researcher in the Department of Physics has developed a novel method for creating high-bandgap materials doped with thorium-229, enabling the development of advanced nuclear clocks. Background: Thorium-229 is the only known isotope with a nuclear transition low enough to be measured using conventional optical techniques. The combination...

Published: 10/9/2025 | Inventor(s): Eric Hudson

Keywords(s): Clock Signal, high-powered laser systems, Laser, laser alignment, Laser Diode, lasers

Category(s): Materials, Materials > Functional Materials, Optics & Photonics, Optics & Photonics > Lasers, Electrical, Electrical > Electronics & Semiconductors, Electrical > Signal Processing, Electrical > Sensors, Electrical > Instrumentation, Electrical > Quantum Computing, Energy & Environment, Energy & Environment > Thermal, Materials > Nanotechnology, Materials > Fabrication Technologies, Materials > Semiconducting Materials

A Radix-3 Network Architecture for Boundary-Less Hierarchical Interconnects (Case No. 2013-162)

Summary UCLA researchers have developed a method for designing and implementing boundary-less hierarchical interconnect networks — switching architectures that reduce path length and routing complexity by transforming conventional hierarchical switch networks into “boundary-less” (or more flexible radix) topologies, enabling improved...

Published: 9/23/2025 | Inventor(s): Dejan Markovic, Chengcheng Wang

Keywords(s):

Category(s): Optics & Photonics, Electrical, Electrical > Electronics & Semiconductors, Electrical > Signal Processing

Fine-Grained Power-Gating Circuitry in FPGA Interconnects (Case No. 2013-181)

Summary UCLA researchers have invented a method and circuit architecture for fine-grained power gating within FPGA (field-programmable gate array) interconnects. By selectively disabling (power gating) unused multiplexers and routing segments at a fine granularity, the approach reduces leakage power in FPGA interconnects while preserving performance...

Published: 9/23/2025 | Inventor(s): Chengcheng Wang, Dejan Markovic

Keywords(s):

Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Signal Processing, Electrical > Computing Hardware, Materials, Materials > Semiconducting Materials

Nanocomposite Scintillators (Case No. 2024-203)

Summary UCLA researchers have developed a nanocomposite scintillator material combining high-atomic-number (high-Z) nanoparticles embedded in a plastic (polymer) matrix, with tunable nanoparticle loading, that delivers higher light output and ultrafast emission (nanosecond-scale) while maintaining low background radiation and environmental stability,...

Published: 9/15/2025 | Inventor(s): Qibing Pei, Ziqing Han, Isabelle Winardi

Keywords(s):

Category(s): Electrical, Electrical > Electronics & Semiconductors, Materials, Materials > Nanotechnology, Materials > Functional Materials, Optics & Photonics, Optics & Photonics > Spectroscopy

Phonon Bridge Layers for Enhanced Thermal Boundary Conductance (Case No. 2024-033)

Summary UCLA researchers have developed a semiconductor device that incorporates a phonon bridge layer between the semiconductor layers and the gate electrode, topped with a diamond layer, aimed at enhancing thermal performance and device stability. In this architecture, the gate electrode is embedded in the phonon bridge layer and contacts the underlying...

Published: 9/11/2025 | Inventor(s):

Keywords(s):

Category(s): Optics & Photonics, Electrical, Electrical > Signal Processing, Electrical > Electronics & Semiconductors

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